1. Field of the Invention
The present invention relates to a low voltage differential signaling (LVDS) driving apparatus, and more particularly, to a LVDS driving apparatus with low operation power.
2. Description of Related Art
FIGS. 1 and 2 show a conventional configuration of an LVDS driving circuit. The conventional LVDS driving circuit sets in the receiving end 17 includes four transistors 10, 11, 12, 13, and two current sources 14, 15, as shown in FIGS. 1 and 2. The ON/OFF status of the transistors 10 and 13 are controlled by the control signals S1, and that of the transistors 11 and 12 are controlled by the control signals S2. When the control signal S1 is LOW and S2 is HIGH, transistors 11 and 12 are ON and transistors 10 and 13 are OFF. Thus, a downward current is produced at the resistor 16 of the output-end 17 and an output logic “1” is produced based on the download current, as shown in FIG. 1. When the control signal S1 is HIGH and S2 is LOW, transistors 11 and 12 are OFF and transistors 10 and 13 are ON. Thus, a upward current is produced at the resistor 16 of the output-end17 and an output logic “0” is produced based on the upload current, as shown in FIG. 2.
However, the power source VDD of the conventional LVDS driving circuit has to meet the limitation that VDD>ΔV14+ΔV15+IrefRL+ΔV11+ΔV12, wherein ΔV14 and ΔV15 are voltage drop of the current sources 14 and 15 respectively, and ΔV11 and ΔV12 are drain-to-source voltage drop of the transistors 11 (or 10) and 12 (or 13) respectively. That is, the minimum operational power VDD of the LVDS driving circuit must be no smaller thanΔV14+ΔV15+IrefRL+ΔV11+ΔV12, which is a relative large operational power requirement in a common integrated circuit. In addition, a complicated control circuit is needed to precisely control the current sources 14 and 15 such that the output current of the current sources 14 and 15 can be substantially the same.